Machine Level Architecture (Part 2 of 2)

Continuing on from my post about the CPU and Processor, there are four main factors that affect the speed of the CPU.  Clock speed refers to 'ticks' of an internal clock, often one but possibly more per instruction.  A faster clock results in instructions being executed at a faster rate, making the processor faster.  Bus width refers to the number of wires that the bus (in the context the data bus) is comprised of.  A wider bus results in a faster data transfer rate, data being broken down into fewer pieces and faster performance overall.  Word length is the number of bits passed through the bus, and is often 32 or 64 bit.  Large words are broken down into pieces to be transmitted through the bus.  Lastly, if the CPU contains multiple processors this results in a greater number of instructions being conducted in the same amount of time.  For example if a CPU contains two cores then it will be able to do the same amount of operations in half of the time that a CPU of the same clock speed with one core takes.

Machine Code Operations refer to operations in binary which are conducted on other binary numbers.  High level programs such as Virtual Basic are converted into Machine Code, and executed.  The machine code instructions will be comprised of an operation code (the instruction itself) and the operand (the subject of the operation).  Each operation code has a unique binary number.  There are three main operations:
-LOAD: load data from a specific memory location, and clear the current accumulator value (e.g. LOAD 5 would correspond to loading data from memory location 5).
-STORE: store the accumulator's current value in a memory location (e.g. STORE 5 would correspond to storing the accumulator's value in memory location 5, wiping the memory location's previous location).
-ADD: add to the total currently stored in the accumulator; may be a real number in which case a # is used (e.g. ADD #5) or a number from a memory location (e.g. ADD 5).

  These instructions as well as others form the Fetch/Execute cycle in the CPU.  Instructions are fetched (obtained) from main memory, and decoded (converted so that they can be understood by the processor), then executed.  This cycle is made up of registries:
-Program Counter: contains the address of the subsequent instruction
-CIR: stores instructions in use during decoding and execution
-MAR: stores the address of the memory being accessed by the processor at that point
-MBR: contains data being transferred to or from the memory address contained in the MAR
-Accumulator: contains the output of the instructions after execution

They are often written in a notation like below (inequalities are used as arrows):
-PC + 1 < PC
-PC < [PC] + 1
-MAR < [PC]
-MBR < [MAR]
-CIR < [MBR]
-ACU < [CIR}